Zener Voltage Regulator

A circuit often introduced in beginning electronics is the zener regulator circuit.  The zener regulator is a simple circuit for providing a constant DC voltage supply, and also a great way to learn more about how a zener diode works.

The idea with the zener regulator is to take advantage of the breakdown behavior of the zener diode.  In the zener diode I-V characteristics curve shown below (note: ignore the numerics, just observe the shape and relationships), when the diode is reverse-biased beyond a negative threshold voltage, the negative zener current flushes out of the gates.  The zener diode is doing all it can to hold the output voltage at the output level for the device, even in the face of large input voltage.  There key here is that the zener diode is reverse-biased and operating in its breakdown mode.

Diode I-V characteristic curve (wikibooks)

This lab will have both a SPICE model and a practical circuit demonstration.  To keep things simple, the input voltage will be +9V DC, which anyone can obtain with a simple 9V battery.  For the zener diode device, I selected a 1N4278, which is a 3.3V zener diode rated at 1W.  In order to select the right value for the resistor, I consulted the 1N4278 datasheet for the values Vz and Iz.  Vz for the 1N4278 is of course 3.3V, and Iz, the breakdown current threshold, is 76 mA.  With these values I could then calculate the acceptable resistor value.

(V – 3.3 V / R) >= Iz
R <= (9.0V – 3.3V) / 76mA
R <= 75 ohms

The resistor needs to be under 75-ohms, plus or minus our tolerances.  From my resistor grab bag, I selected a 47-ohm resistor to begin the experiment.

SPICE simulation

To model this circuit with SPICE, we only need three components: the input source, the resistor, and the zener diode.  The SPICE model for MacSpice is shown below.

* Zener Diode Voltage Regulator
Vin 1 0 DC 9V
R1 1 2 47
D1 0 3 zener
.model zener D (BV=3.3)
.control
dc Vin 0 9 0.5
print v(1) i(Vm) v(2)
.endc
.end

The SPICE model performs a DC sweep on the 9V input source, starting from 0V and increasing to +9V in 0.5V increments.  The output of the DC sweep is shown below.

Circuit: * Zener Diode Voltage Regulator

                        * Zener Diode Voltage Regulator
             DC transfer characteristic  Mon May 16 23:30:20  2011
--------------------------------------------------------------------
Index     sweep         v(1)          v(2)
--------------------------------------------------------------------
0         0.00000e+00   0.00000e+00   -2.51984e-35
1         5.00000e-01   5.00000e-01   5.00000e-01
2         1.00000e+00   1.00000e+00   1.00000e+00
3         1.50000e+00   1.50000e+00   1.50000e+00
4         2.00000e+00   2.00000e+00   2.00000e+00
5         2.50000e+00   2.50000e+00   2.50000e+00
6         3.00000e+00   3.00000e+00   3.00000e+00
7         3.50000e+00   3.50000e+00   3.33298e+00
8         4.00000e+00   4.00000e+00   3.36744e+00
9         4.50000e+00   4.50000e+00   3.38260e+00
10        5.00000e+00   5.00000e+00   3.39209e+00
11        5.50000e+00   5.50000e+00   3.39849e+00
12        6.00000e+00   6.00000e+00   3.40378e+00
13        6.50000e+00   6.50000e+00   3.40829e+00
14        7.00000e+00   7.00000e+00   3.41213e+00
15        7.50000e+00   7.50000e+00   3.41548e+00
16        8.00000e+00   8.00000e+00   3.41845e+00
17        8.50000e+00   8.50000e+00   3.42112e+00
18        9.00000e+00   9.00000e+00   3.42353e+00

As can be seen from the output, when the input source is reaches a level above +3.3V, the zener diode, which is reverse biased, see this as -3.3V and opens the flood gates for the zener current.

Demonstration

In the picture below, the 47-ohm resistor is the horizontal device, and the diode is the vertical device to the right.

Output of the zener regulator

I hooked up my multimeter to the output port of the zener regulator, as expected enough the output voltage was 3.309V.  With such a large voltage drop over the small 47-ohm resistor, it heats up very quickly; after all, that difference in energy has to be dissipated somehow, and the resistor dissipates energy via heat.

What if we hooked up a potentiometer to the output of the circuit?  I had a 10k-ohm potentiometer in my toolbox, so I hooked it up to the output of the zener regulator.

Potentiometer hooked up to zener regulator output

I started at zero ohms and slowly turned the dial.  The zener regulator was able to hold the output voltage until I had turned the dial about three-quarters of the way, or roughly 7.5k-ohm.  The output dropped to 0.556V.

And what if I swapped the 47-ohm resistor and the  potentiometer?

Potentiometer between zener diode and input source

Unless I had the dial almost completely at the zero position, the zener diode was not able to regulate 3.3V, as shown above.  The resistor between the zener diode and the input source must be small enough to meet the threshold Iz from the datasheet.

Conclusions

Both the SPICE simulation and practical demonstration backed up the theory of the zener diode as depicted by the I-V characteristic curve.  The regulator circuit provides a steady 3.3V DC while operating under the correct parameters.  For practical regulator circuits, however, the zener regulator is quite in efficient and dissipates a lot of energy through heat in the resistor.  For simple lab experiments and learning purposes, however, the zener regulator is a convenient and simple way to create a fixed DC voltage supply.  Of course it is easier to purchase a few three-terminal linear regulators as well, such as the LM series regulators (3V, 5V, 6,V, 9V, etc.)

For more on the zener diode and regulator circuit, make sure to check out All About Circuit’s page on zener diodes and WikiBooks.

My First ASIC

For the first time in the past few years, I’m really having a lot of fun, and I owe it to my ASIC design course.  For a previous homework assignment, I had to modify and customize a simple counter device.  I then had to simulate and find the optimal clock period with Synopsys.  In the next homework assignment, I had generate the back-annotated delays, and then re-simulate, re-synthesize, and finally analyze for power consumption.  Using the Cadence Encounter tool that is available on campus, the result of my efforts is shown below.

My First ASIC - a simple counter

 

Now I just have to learn how to read what Encounter is showing me (Fence, Guide, Obstruct, etc.) …

XP2 Board: Clock, Power and Reset Subsystems

Power Supply Subsystem

The XP2 Brevia Board is powered by an AC adapter connected on J6 jack.  The AC adapter converts the AC voltage to a 6V, 1 A DC voltage.  This DC input is then fed into two National LM117 voltage regulators.  According to the LM117 data sheet, the out voltage ranges from 1.2 to 37 at 1.5 A and is configurable using resistors in the output feedback loop.  The output is computed using the following equation:

Vout = Vref (1 + R2/R1) + Iadj*R2

As per the data sheet, Vref is a fixed 1.25 V, and Iadj is a small fixed current.  In the equation above, the Iadj part is small enough to be ignored for practical purposes.  For the 1.2 V output, “R2″ is R22, a zero ohm resistor, and thus the output voltage is equal to Vref.  This is within the tolerance of the FPGA core voltage, the input voltage required to power the core parts of the FPGA: the LUTs, flip-flops, mux, etc. that make up the logic cells.

For the 3.3 V output, “R2″ is R24 and “R1″ is R23.  R2/R1 is 1.65, which when added to 1 and multiplied by Vref provides about 3.3V volts.  This 3.3V is actually Vio, the voltage required for the FPGA input and output pads.  Most FPGAs usually have two voltage supplies: the core and I/O voltages.  FPGAs with high speed serial transceivers–SERDES–often have a separate supply for these transceivers.

On the schematic also note the capacitors C26-C32 and C37-C45 placed respectively between the 1.2V and 3.3V regulated output and ground.  C27-C45 are shown below as in the schematic.

These are decoupling capacitors, usually inserted between an IC voltage input and ground so that when the IC draws large currents and the voltage supply level temporarily drops, the capacitors discharge their stored energy in and effort to keep the voltage level constant.  The capacitors are often drawn this way in industry so as not to clutter the schematic near the ICs.  This style does make it easier for FPGA, micro-controller, or microprocessor developers to focus on the I/Os around the device.

Another interesting section of the schematic on the page with the DC regulators is the ground-ground connection:

Often this is a notation to mark that the digital and analog ground planes are to be joined by a connection so that both analog and digital share the same ground plane.

Clock Subsystem

A 50 MHz square wave output oscillator (select the H22/H32/H53/SWO datasheet), X1, is on the circuit board and will act as the reference clock in the FPGA.  The output of the oscillator, XOUT, is directly connected to the FPGA and there is not really anything interesting in this clock subsystem, except for C8 attached between the XOUT signal and ground.  C8 is a load capacitor, and for  more information on load capacitors on the output of an oscillator, consult the manufacturer’s technical note Effect of Load Capacitance on the Crystal.

We will do more with the clock signal once we start working with the innards of the FPGA.

Global Reset Subsystem

The XP2 board has a reset push-button, S1, that when pushed resets the FPGA to an initial state.  The circuit for the reset is shown below:

The circuit attached to the output of the push-button S1 is a simple analog debouncing circuit.  A debounce circuit is necessary because it prevents spurious noise from accidentally resetting the system.  Conceptually, the debounce circuit is very easy to understand.  When 3.3V is supplied and the push-button is depressed, the RESET and signal is a logical ‘high’ or ’1′ value, and capacitor C13 begins to charge.  Remember that the time required for the capacitor to discharge is roughly 5*T, where T=R19*C13.  When the push button is pressed it causes the current from 3.3V to travel the path of least resistance to ground.  In other words, the RESET signal is pulled-down to ground.  Capacitor C13 resists voltage changes, and starts to discharge its stored energy in an futile attempt to keep the voltage levels the same.  After about 5*T, the capacitor will be completely discharged and RESET sits at ‘low’ or ’0′ value.  The following is a simple SPICE (MacSpice) model that shows the level of RESET: the switch is initially open, and then at t=1ms the push-button is pressed and held down.

* Analog Switch Debouncing
* Use a pulse to emulate the behavior of an analog switch pulling-down input voltage
V1 1 0 PULSE(0 3.3 2ns 2ns 2ns 1ms 2ms)
R1 1 2 10k
C1 2 0 10n ic=0
.control
tran .005 .002 uic
plot v(2)
.endc
.end

V(2) is the equivalent of the RESET signal in the circuit schematic above.

Because the push-button must be depressed longer than 5*T, sudden spikes and instantaneous signals on the RESET line will not cause the FPGA to be reset.  For this circuit, under ideal circumstances, T=10k*10nF=100us, and 5*T is 500us.  For modern FPGAs and digital circuits, 500us is an eternity!  Only a purposeful reset will make its way to the FPGA.  Note also that the signal XP2_RESET is connected to RESET by a zero ohm resistor R20.  XP2_RESET goes to the external connector J4 pin 39 so that an FPGA on one board will travel to any external connections to J4.  XP2_RESET can be disabled by removing R20 from the circuit board if desired.

Conclusion

Now that we understand the power, clock and reset sub-systems, we are ready to begin experimenting with the FPGA itself.  The next step is to setup the clock and reset signals inside of the FPGA.

Emitter-follower: Lab 4.2

This lab covers the basics of the emitter-follower configuration of the BJT transistor.  The lab is based on the circuit in Student Manual for the Art of Electronics Lab 4-2. Note that the emitter-follower is also known as the common-collector.  The output is taken at the emitter, the input is provided at the base, and the voltage gain is roughly equal to one (Vemitter / Vin). Note that in this circuit, the input resistance is much smaller than the output resistance.  This is what the authors of the book decided on, but in most practical circuits the emitter-follower is used to bridge a high-impedance input to a lower impedance load.  According to Horrowitz and Hill, “…the emitter follower is useful for changing impedances of signals or loads.  To put it bluntly, that’s the whole point of the emitter follower.”

The following Spice model represents the circuit from the lab, and the Spice syntax is that of MacSpice.

* Emitter Follower Lab
Vcc 3 0 DC 15
Vin 1 0 SIN(0 5 60)
R1  1 2 270
R4  4 0 3.3k
Q1  3 2 4 generic
.model generic npn
.control
tran 1ms 60ms
plot v(1) v(4)
.endc
.end

The resulting output:  v(1) is the input and v(4) is the output at the emitter

The signal Vin at the base is expected to be the same at the emitter.  The amplitude of the signal on the emitter should be 0.6V different from the base signal due to the base-emitter junction voltage drop.  As shown above, the Vin is 5 V and the emitter amplitude is around 4.3 V.  However, when the signal swings below zero the output is clipped.  Why is that?

The reason is that when Vin swings below 0.6/0.7 V, the base-emitter voltage difference falls below the threshold and goes into to cutoff mode due to the reverse bias of the junction.  When the input voltage at the base rises above 0.6V again the transistor is enabled and passes the signal to the emitter.

One way to pass the negative part of the input signal is to have the input within the range of the trainsistors supply, Vcc – Ground (15 V – 0).  This can be done by having the input source centered around a DC offset greater than 5 V or by providing a bias network at the base of the transistor to bring the original signal up.  For simulating just modify the Spice model so that Vin is centered around 7.5 V DC rather than 0 V DC.  Just modify the first parameter of the SIN function as follows:

Vin 1 0 SIN(7.5 5 60)

The resulting output:  v(1) is the input and v(4) is the output at the emitter

Now the output looks like the input, minus the small voltage drop caused by the base-emitter junction.

The lab also asks us to hook up the emitter to a negative supply (-15V) instead of ground.  The SPICE model below presents just such a circuit.

* Emitter Follower Lab with Negative Supply Vee
Vcc 3 0 DC 15
Vee 0 5 DC 15
Vin 1 0 SIN(0 5 60)
R1  1 2 270
R4  4 5 3.3k
Q1  3 2 4 generic
.model generic npn
.control
tran 1ms 60ms
plot v(1) v(4)
.endc
.end

The resulting output:  v(1) is the input and v(4) is the output at the emitter

The output in this case is the same as the centered input.  The difference is that in practical circuits, one often doesn’t have control over the DC offset of the input signal.  In such cases, either a negative supply is needed to catch the negative swing of the input signal, or a bias network is needed at the base.  Such a bias network is reviewed in Lab 4.4.

Biased Emitter Follwer: Lab 4.4

Art of Electronics Student Manual Lab 4.4 presents a biased emitter-follower (common-collector) amplifier circuit with a single supply Vcc=+15V.  The amplifie5 is biased using Vcc and causes the input AC signal to oscillate around +6V rather than 0V.  By biasing the transistor, we make sure the input stays with the range of the active region of the transistor.

The purpose of this lab is to increase the peak-to-peak voltage of the input AC signal and observe the effects on the output signal as the the voltage swing is increased.  Before starting the lab, however, it is important to think about what might happen as the voltage increases.  If the voltage at the base is larger than than the voltage at the collector of the transistor, the collector-base junction should be forward biased.  If the voltage at the emitter is larger than the voltage at the base, the emitter-base junction should also be reversed, causing the output signal to be pulled to ground.

The MacSpice model for the circuit in the lab is as follows:

* Art of Electronics Lab 4.4
Vin 1 0 SIN(0 5 60)
C1 1 2 1u
R1 4 2 130k
R2 2 0 150k
Vcc 4 0 DC 15
Re  3 0 3.3k
Q1  4 2 3 generic
.model generic npn
.control
tran 1ms 60ms
plot v(1) v(4) v(3)
.endc
.end

Results:

For a 5V swing, the output is as follows: v(1) – input, v(4) – Vcc, V(3) – output

The 5V signal centered around 6 V produces a swing of 1v <= Vin <= 11 V, which is well within the 15V supply.  The output signal at the emitter resembles Vin, with the same phase and nearly the same amplitude, minus the base-emitter voltage drop of around 0.6~0.7V. Lets increase the voltage swing.

For a 10V swing, the output is as follows: v(1) – input, v(4) – Vcc, V(3) – output

The voltage swing in this circuit is -4V <= Vin <= 16 V minus the base-emitter junction voltage drop.  Notice the clipping in this circuit, particularly when Vin < 0V, the output clips because the base-emitter junction is reversed biased and the transistor goes into cutoff mode.  Essentialy, when Vbase – Vemitter < 0.6/0.7 V, the transistor shuts off.  For this circuit, the input is centered around ground, and the bias brings it up to 6V.  Were it not for the bias, the input signal would be clipped at the output for all of the negative cycle of the input signal.  As we can see, when the base-emitter junction is reverse biases, it pulls the output voltage at the emitter through R3 to its rail, in this case ground.  Lets increase the swing again.

For a 15V swing, the output is as follows: v(1) – input, v(4) – Vcc, V(3) – output

Notice the clipping is extreme in the negative cycle, but it is also present at the peak of the positive cycle of Vin.  In the positive cycle, when Vbase > Vcollector + 0.6/0.7 V, the junction is becomes forward-biased and the output cannot swing above the collector, which is fixed at the supply (Vcc).

So what does this lab help us understand?  The lab shows that when using the emitter follower, we must design the amplifier output to fall within the limit of the positive supply (Vcc) as well as the emitter termination.  We can use a bias network and a single supply (Vcc) to center our input signal within the range of the amplifier.  We must be mindful of the input range, always!

Getting Started with Electronics

So while my FPGA series is paused, I have decided to try to take a new direction (again).  I start my Master’s degree in Electrical Engineering next week, and I have two demons two face. I am determined that I will defeat these demons this time.

My first demon is electromagnetics, which I plan to challenge again in the near future.  I originally took the course over seven weeks during the summer, alongside with chemistry and another course.  As a result, in such a shot time I could not focus solely on electromagnetics, and being as stupid as I am, I really could not wrap my head around the subject.  None of the chapters connected and I was really lost.  Once I entered the workforce and started working in an antenna research division of a company, I understood the broad aspects very well.  Now that I understand the RF world, S-parameters, and antenna fundamentals, I would like to go back and challenge Maxwell’s equations, TEM modes, and all of the other stuff that I just could not understand as an undergraduate.

My second demon is analog electronics.  During my undergraduate degree, I had to take an electronics course that turned out to be a nightmare.  Though I did perfectly well in the laboratory portion, I did not fair so well in the lecture portion of the course.  I attribute this to the fact that I was too distracted by the mathematics and silly models to see the big picture.  Also it did not help that the course was taught by a physicist who was more interested in the physics of transistors than their application.  As a result of this course, I steered myself towards digital electronics rather than analog electronics.  It was not until I started my career that I would understand how simple transistors can be utilized in circuits.

Even after starting my career, I worked strictly in the digital domain, so the only raw transistors I used were digital transistors used for switching ICs on and off.  Of course the ICs, ASICs and FPGAs I used were powered by MOSFETs, but they were abstracted away from me.

I want to understand BJTs and FETs better, especially in the analog domain of amplification rather than switching.  I cannot afford to set up an electronics lab with function generators and oscilloscopes, so I will instead use a SPICE simulator.  With a textbook (Art of Electronics), simple analog circuits and SPICE output, I hope to get a better understanding of how analog circuits work.  I will post the SPICE models, schematics, and the output of my lab experiments so that I can make sure I understand everything and also share what I have learned.