On Verilog compilers

I’ve been working on my term project for my ASIC design course, and one thing I find very disturbing is the difference in error discovery between various Verilog compilers.  My design compiled correctly with ModelSim’s vlog compiler, but GNU Icarus Verilog caught errors that ModelSim did not.  After fixing the issues I then ran my Verilog through Synopsys Design Compiler so that I could synthesize the design.  Interestingly, Design Compiler caught some rather serious bugs that both ModelSim and Icarus missed.

If I ever start my own chip design company, I will definitely invest in a Synopsys license!  It would also be interesting to run the verilog model with the errors through FPGA Verilog compilers like Xilinx or Lattice and see if those tools can catch the same errors as Design Compiler.  I have no time for that right now though…

FPGA in a CPU

Embedding a CPU via IP cores has long been popular in the world of FPGAs and ASICs.  In these times of the System-on-Chip (SoC), most large designs require a microprocessor to aid in speeding up development cycles, easing complexity, and improving time to market.  But what about CPUs with embedded FPGAs?

NetworkWorld is reporting that Intel will be embedding an Altera FPGA into the Atom E600 microprocessor.  The Atom is an Intel processor aimed at embedding computing platforms and portable devices like netbooks.  How are Intel going about doing this?  According to NetworkWorld,

In the E600C series, Intel attached the Altera FPGA to the E600 via a standard PCI Express connection with two lanes. Luse declined to comment on if or when Intel might manufacture the Atom and FPGA on a single die.

This has potentially interesting applications.  Instead of designing a separate PCIe card, engineers can now implement their design inside the CPU, reducing the need for other areas of design work, such as power circuitry, PCIe interface and circuit board layout. Designs with a PCIe interface can also be reused between regular FPGAs on a circuit board and embedded FPGAs.  While I don’t see such embedded FPGAs replacing FPGAs as they are today, I do see the potential for creating domain or application specific co-processors in the embedded FPGAs, for example, encryption engines.

I am curious about whether or not there will be an external I/O interface that connects directly to the FPGA.  I also wonder what type of clock speeds we can expect for the embedded FPGAs?

RapidIO Vendor ID List

Just for reference in case any else is looking for it, the vendor ID list for the various RapidIO parks makers is available at the RapidIO Specs web site.  Just like with PCI and USB, RapidIO uses device and vendor IDs to differentiate devices in a system.

Welcome

Welcome to The Global Engineer’s Notebook. I hope to keep this online journal for the purpose of sharing things I learn and sharing my experiences. I hope that young engineers will be able to see that you don’t just know it all, you learn through experimentation, trial and error.