GNU Verilog

I started my graduate studies in electrical engineering on this past Monday.  I am taking a course in ASIC design which I have always wanted to learn more about.  In the course we will be using the Verilog HDL language, and we will be using expensive industry standard tools, including  ModelSim for simulation and Synopsis for synthesis.  I do not always have access to ModelSim and I was looking for a simple way to test some verilog without having to use the university’s machines.  I stumbled upon the GNU Icaraus Verilog compiler and GtkWave.  Like all GNU tools, they are available free of charge and are of rather good quality in my opinion.  I created a basic tutorial for getting started with these tools using a simple D flip-flop.

Before getting started, one must install the ‘verilog’ and ‘gtkwave’ packages, corresponding to Icarus Verilog and GtkWave.  I found the packages available for OpenSuSE, and I am sure they are also available for other distributions too.  The brave can alawys build from the source if no package exists.

Lets get started.  Below is the verilog model for a simple D flip-flop with a synchronous reset.

// dff.v
module dff(d,q,clock,reset);
input wire clock;
input wire reset;
input wire d;
output reg q;

always @(posedge clock)
begin
if (clock) begin
if (reset) begin
q <= 1’b0;
end
else begin
q <= d;
end
end
end

Below is a basic test bench with a 20 ns clock period that toggles the flip-flop input a few times.

// dff_tb.v
`timescale 1ns/1ps
module dff_tb;
parameter CLK_PERIOD = 20;
reg clock, reset, d;
wire q;

dff d0(
.d(d),
.q(q),
.reset(reset),
.clock(clock)
);

initial begin
$dumpfile(“dff_tb.vcd”);
$dumpvars(1, dff_tb);
$monitor(“clock=%b, d=%b, q=%b”, clock, d, q);
clock = 1’b1;
reset = 1’b1;
d = 1’b0;
#(CLK_PERIOD*5)
reset = 1’b0;
#CLK_PERIOD
d = 1’b1;
#CLK_PERIOD
d = 1’b0;
#CLK_PERIOD
d = 1’b1;
#CLK_PERIOD
d = 1’b0;
#CLK_PERIOD
$finish;
end

always #(CLK_PERIOD/2) clock = ~clock;

endmodule

The test bench is written such that the changes in the signals are dumped to a Value Change Dump (VCD) file, using the $dumpfile and $dumpvars system commands.  The state of the variables is also printed to the terminal using the $monitor system command. Now that the D flip-flop module and a test bench are ready, we need to compile the verilog and run the simulator.

iverilog -o dff dff.v dff_tb.v  # compiles the modules into a “dff” project
vvp dff                                           # runs the simulation on the project
gtkwave -f dff_tb.vcd              # graphically view the simulation output

Selecting the dff_tb in the upper lefthand box, add each of the four signals using the “insert” button.  The time scale will probably set set in the picoseconds, so zoom out until you are at a suitable scale to view the waveforms.  This can all probably be done on the command line, but I have not looked into it yet.

As you can see, with two very simple packages it is easy to get started modeling with Verilog–with no cost at all.  Synthesis, on the other hand…

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