The Power of Synthesis

When I was an undergraduate a lot of my classmates hated HDLs (we were learning VHDL).  They often claimed they were electronic engineers and not programmers, they hated writing programs and wanted to work with circuits and electronics.  It probably did not help that the professors loved to give academic problems rather than real-world issues.  I think more would have enjoyed learning HDLs and RTL if they had been interfacing FPGAs with other components or designing digital filters rather than implementing LZH compression algorithms in hardware and software.  However, I also think they failed to see the true power of HDLs and hardware synthesis.

What my fellow classmates did not realize is that even though they were writing RTL in a programming language-like syntax, they were actually designing circuits.  I suspect the compilers and the for-loops may have thrown them off, but they were really modeling hardware.  One doesn’t just begin writing RTL (without years of experience at least), one has a high -level circuit in mind that should be modeled with the RTL.  Take the following Verilog RTL, for example, with a for-loop:

module bitmask(
  input clock,
  input [7:0] in_data,
  input [3:0] index,
  output [7:0] sum

reg [7:0] buffer;
reg [7:0] mask;

assign sum = buffer;

always @(posedge clock)
  buffer <= mask & in_data;

integer i;

always @(*)
  for(i=7; i>=0; i=i-1)
    mask[i] = (i>= index) ? 1'b0 : 1'b1;


For those that don’t read Verilog or just refuse to try, this module applies an adjustable mask to an input and stores the result in a register.  The mask is created by specify from where the mask should begin.  The result of a simulation is shown below.  Note that in the output below, ptr maps to index and data maps to in_data

GtkWave display of the value-change dump (generated by GNU Icarus Verilog)

The incoming data is 0x55h, and the mask ptr is set to 4.  In terms of big endianness, this means that the lower byte of the mask should be all ones and the upper byte should be all zeros.  The result when the register clocks the masked data on the clock’s positive edge is 0x05h.  We then change the input data to 0xDEh, and the mask ptr is set to 5.  Now the mask consists of the top three bits being zeros, and the lower five bits being ones.  On the positive clock edge, the result in the register is 0x1Eh.

This is a very primitive example, but I wanted to show how some simple RTL modeling can be so powerful.  I synthesized this module using Synopsys Design Compiler one of my university’s lab machines.  The synthesized circuit is shown below.   I was synthesizing with an ASIC standard cell library, so if you did this for an FPGA you might get somewhat different output.

Unfortunately, Synopsys did not print the port names when the schematic was exported to postscript, but I think you can get the idea.  The squares on the right are the flip-flops that correspong to register buffer.  The ports of the left represent the inputs, and the logic gates between the inputs and flip-flops are the combination logic required to produce the mask.

The true power of synthesis is that it allows designers to increase their productivity in great strides.  While it may take only a few minutes to model a circuit with RTL and do a quick simulation for verification, imagine having to do karnaugh-map optimizations and truth-tables to come up with the optimized circuit that Synopsys produced?

XP2 Board: Clock, Power and Reset Subsystems

Power Supply Subsystem

The XP2 Brevia Board is powered by an AC adapter connected on J6 jack.  The AC adapter converts the AC voltage to a 6V, 1 A DC voltage.  This DC input is then fed into two National LM117 voltage regulators.  According to the LM117 data sheet, the out voltage ranges from 1.2 to 37 at 1.5 A and is configurable using resistors in the output feedback loop.  The output is computed using the following equation:

Vout = Vref (1 + R2/R1) + Iadj*R2

As per the data sheet, Vref is a fixed 1.25 V, and Iadj is a small fixed current.  In the equation above, the Iadj part is small enough to be ignored for practical purposes.  For the 1.2 V output, “R2” is R22, a zero ohm resistor, and thus the output voltage is equal to Vref.  This is within the tolerance of the FPGA core voltage, the input voltage required to power the core parts of the FPGA: the LUTs, flip-flops, mux, etc. that make up the logic cells.

For the 3.3 V output, “R2” is R24 and “R1” is R23.  R2/R1 is 1.65, which when added to 1 and multiplied by Vref provides about 3.3V volts.  This 3.3V is actually Vio, the voltage required for the FPGA input and output pads.  Most FPGAs usually have two voltage supplies: the core and I/O voltages.  FPGAs with high speed serial transceivers–SERDES–often have a separate supply for these transceivers.

On the schematic also note the capacitors C26-C32 and C37-C45 placed respectively between the 1.2V and 3.3V regulated output and ground.  C27-C45 are shown below as in the schematic.

These are decoupling capacitors, usually inserted between an IC voltage input and ground so that when the IC draws large currents and the voltage supply level temporarily drops, the capacitors discharge their stored energy in and effort to keep the voltage level constant.  The capacitors are often drawn this way in industry so as not to clutter the schematic near the ICs.  This style does make it easier for FPGA, micro-controller, or microprocessor developers to focus on the I/Os around the device.

Another interesting section of the schematic on the page with the DC regulators is the ground-ground connection:

Often this is a notation to mark that the digital and analog ground planes are to be joined by a connection so that both analog and digital share the same ground plane.

Clock Subsystem

A 50 MHz square wave output oscillator (select the H22/H32/H53/SWO datasheet), X1, is on the circuit board and will act as the reference clock in the FPGA.  The output of the oscillator, XOUT, is directly connected to the FPGA and there is not really anything interesting in this clock subsystem, except for C8 attached between the XOUT signal and ground.  C8 is a load capacitor, and for  more information on load capacitors on the output of an oscillator, consult the manufacturer’s technical note Effect of Load Capacitance on the Crystal.

We will do more with the clock signal once we start working with the innards of the FPGA.

Global Reset Subsystem

The XP2 board has a reset push-button, S1, that when pushed resets the FPGA to an initial state.  The circuit for the reset is shown below:

The circuit attached to the output of the push-button S1 is a simple analog debouncing circuit.  A debounce circuit is necessary because it prevents spurious noise from accidentally resetting the system.  Conceptually, the debounce circuit is very easy to understand.  When 3.3V is supplied and the push-button is depressed, the RESET and signal is a logical ‘high’ or ‘1’ value, and capacitor C13 begins to charge.  Remember that the time required for the capacitor to discharge is roughly 5*T, where T=R19*C13.  When the push button is pressed it causes the current from 3.3V to travel the path of least resistance to ground.  In other words, the RESET signal is pulled-down to ground.  Capacitor C13 resists voltage changes, and starts to discharge its stored energy in an futile attempt to keep the voltage levels the same.  After about 5*T, the capacitor will be completely discharged and RESET sits at ‘low’ or ‘0’ value.  The following is a simple SPICE (MacSpice) model that shows the level of RESET: the switch is initially open, and then at t=1ms the push-button is pressed and held down.

* Analog Switch Debouncing
* Use a pulse to emulate the behavior of an analog switch pulling-down input voltage
V1 1 0 PULSE(0 3.3 2ns 2ns 2ns 1ms 2ms)
R1 1 2 10k
C1 2 0 10n ic=0
tran .005 .002 uic
plot v(2)

V(2) is the equivalent of the RESET signal in the circuit schematic above.

Because the push-button must be depressed longer than 5*T, sudden spikes and instantaneous signals on the RESET line will not cause the FPGA to be reset.  For this circuit, under ideal circumstances, T=10k*10nF=100us, and 5*T is 500us.  For modern FPGAs and digital circuits, 500us is an eternity!  Only a purposeful reset will make its way to the FPGA.  Note also that the signal XP2_RESET is connected to RESET by a zero ohm resistor R20.  XP2_RESET goes to the external connector J4 pin 39 so that an FPGA on one board will travel to any external connections to J4.  XP2_RESET can be disabled by removing R20 from the circuit board if desired.


Now that we understand the power, clock and reset sub-systems, we are ready to begin experimenting with the FPGA itself.  The next step is to setup the clock and reset signals inside of the FPGA.

XP2 Board: JTAG scan with ispVM

Back in business, and ain’t it grand! So I decided to go with option number two and bring my old PC back to life. I could not stand the though of having to reboot between Mac OS X and Windows.  With the old PC I have not tried to build any designs or run any simulations yet, but the machine should be able to handle it, perhaps quite slowly though.

To continue with my exploration of the XP2 board, I thought it best to make sure that I could see the FPGA in the JTAG programming chain.  JTAG is an simple interface used for testing silicon devices on a circuit board, and it is also a common interface for programming FPGAs during the design and testing phase in the development cycle.  Every FPGA vendor has its own tool for programming devices, and for Lattice FPGAs the tool is ispVM.

Lets get started.  First the XP2 board must be connected to a JTAG programming cable using the J3 connector labeled “JTAG” on the circuit board.  For the parallel port programming cable supplied with the XP2 Brevia Kit, just follow the directions in the QuickStart guide.  For the USB programming cable, note the the names of the different wires, and then use the QuickStart guide to match the wire name to the right pin.

Once the cable is connected correctly, supply power to the XP2 board and launch ispVM.  After it opens, I like to close all of the open windows in the GUI and start fresh, as shown below.

To perform a simple JTAG chain scan, press F2 or select from the menu bar ispTools->Scan Chain.  ispVM reports all of the devices in the JTAG chain connected to connector J1 on the board. For this XP2 Brevia board, the only device is the XP2 FPGA itself.  In more complex designs, it is not uncommon to have several devices in the chain, such as a flash memory for device configuration, FPGAs, CPLDs, and even embedded processors like PowerPC or DSPs.  When the scan is complete, the XP2 FPGA should be visible and the only device:


XP2 FPGA found from the JTAG chain scan

As expected, the device is visible and we have also gained some basic familiarity with the ispVM tool.  With both the serial port verified with the demo program and the JTAG scan completed, the basic connections to the outside world are verified.  Before creating a simple design and programming it to the device, there is one more critical step that requires attention: power and clock systems on the circuit board.  And that shall be the topic of the next post!