Verilog Include files with ModelSim

I am currently using ModelSim to verify some hardware modules for my term project, and I have developed some tasks and macros that are useful when working with SRAM modules.  I decided to put these in a separate file from my testbench code, and then have the testbench code use the `include verilog macro to include these tasks in the testbench.  This has two advantages:

  1. The tasks and macros can be shared and used in other testbenches
  2. The testbench code is significantly easier to read

For those not familiar with the `include macro, from section 19.5 of the IEEE1394-2001 Verilog Language Reference Manual,

The file inclusion (`include) compiler directive is used to insert the entire contents of a source file in another file during compilation. The result is as though the contents of the included source filea ppear in place of the `include compiler directive.

Please note that you can also use `ifndef/`define/`endif macros, just as you would with C/C++ header files, to prevent compiler issues due to multiple inclusions of the included file.  Also like C/C++ compilers, ModemSim’s verilog compiler looks in the current directory for included files.  Any files not in the current directory will not be found by the compiler, as shown below.

> vlog testbench/sram_tb.v
# Model Technology ModelSim PE Student Edition vlog 10.0a Compiler 2011.02 Feb 20 2011
# — Compiling module sram_tb
# ** Error: testbench/sram_tb.v(120): Cannot find `include file “sram_tb_util.v” in directories:
#     C:/Modeltech_pe_edu_10.0a/ovm-2.1.1/../verilog_src/ovm-2.1.1/src, C:/Modeltech_pe_edu_10.0a/uvm-1.0/../verilog_src/uvm-1.0/src
# C:/Modeltech_pe_edu_10.0a/win32pe_edu/vlog failed.

There are two ways to specify the include path.  The first method is to pass the incdir option to the vlog command.  The command below tells the verilog compiler to look in the testbench directory for any files included in the sram_tb.v file.

vlog testbench/sram_tb.v +incdir+./testbench

The other way is to use the GUI to set the include directories for project.  Right-click on any verilog source file in the Project View, and select “Properties…”.  In the dialog box that appears, select the Verilog & System Verilog tab, and use the “Include directories…” button to add paths to include directories.

Whenever you compile your verilog source files, the paths specified in the include directories will be searched when the `include macro is encountered in your source files. Please note that this only works when you compile with the GUI compile button.  Users who prefer to use the command shell in the GUI –like myself–will still have to add the +incdir+ option to the vlog command.  I suppose the designers of ModelSim are encouraging us to write Tcl build scripts…


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