My First ASIC

For the first time in the past few years, I’m really having a lot of fun, and I owe it to my ASIC design course.  For a previous homework assignment, I had to modify and customize a simple counter device.  I then had to simulate and find the optimal clock period with Synopsys.  In the next homework assignment, I had generate the back-annotated delays, and then re-simulate, re-synthesize, and finally analyze for power consumption.  Using the Cadence Encounter tool that is available on campus, the result of my efforts is shown below.

My First ASIC - a simple counter

 

Now I just have to learn how to read what Encounter is showing me (Fence, Guide, Obstruct, etc.) …

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