On Verilog compilers

I’ve been working on my term project for my ASIC design course, and one thing I find very disturbing is the difference in error discovery between various Verilog compilers.  My design compiled correctly with ModelSim’s vlog compiler, but GNU Icarus Verilog caught errors that ModelSim did not.  After fixing the issues I then ran my Verilog through Synopsys Design Compiler so that I could synthesize the design.  Interestingly, Design Compiler caught some rather serious bugs that both ModelSim and Icarus missed.

If I ever start my own chip design company, I will definitely invest in a Synopsys license!  It would also be interesting to run the verilog model with the errors through FPGA Verilog compilers like Xilinx or Lattice and see if those tools can catch the same errors as Design Compiler.  I have no time for that right now though…

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