End of Semester – Still alive and kicking!

This week marked the end of a very intense semester in my graduate program. I had planned to just take Power Electronics and then a business or engineering management-type elective, but a course in advanced ASIC design topics was offered and I signed up. The course was split into two sections: SystemC modeling and then back-end physical design for ASICs. It turned out that both of courses were very intense, and trying to complete all of the course work on top of my full-time job was very challenging. I made it through it all though with solid grades. In the ASIC course, I learned a lot about ARM CPUs, especially the buses (AHB, AXB) that interface with peripheral devices, and I learned a lot about DDR memories too. SystemC was quite interesting, a very interesting way to model a system-on-chip (SoC). As a C++ programmer I really liked working with SystemC!  Most of all though, I thoroughly enjoyed the back-end design: placing standard cells, power/ground networks, clock-tree routing, and data signal wire routing. There are lots of algorithms going on in tools like Synopsys IC Compiler and Synopsys PrimeTime, the clustering and routing algorithms alone are fascinating for those interested in applications of algorithms.

Below is a screen capture of my clock-tree in an ARM CortexM0 design. It reminds me of a fractal in some ways! All in all it was a really useful course, and working with ASICs always makes me think about trying to find a job in the semiconductor industry…fascinating technology.

proj3_clock_tree

I plan to finish the program and “graduate” at the end of the next semester. I willl take a course in VLSI system design as well as a managerial accounting course. Yes, I am backing down and taking a business course! I learned my lesson this semester with two engineering courses, it was just so intense. VLSI will be a great course, and I think that an accounting course would at least be useful knowledge.

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My First ASIC

For the first time in the past few years, I’m really having a lot of fun, and I owe it to my ASIC design course.  For a previous homework assignment, I had to modify and customize a simple counter device.  I then had to simulate and find the optimal clock period with Synopsys.  In the next homework assignment, I had generate the back-annotated delays, and then re-simulate, re-synthesize, and finally analyze for power consumption.  Using the Cadence Encounter tool that is available on campus, the result of my efforts is shown below.

My First ASIC - a simple counter

 

Now I just have to learn how to read what Encounter is showing me (Fence, Guide, Obstruct, etc.) …