NCVerilog Tutorial: Configuration

The first thing to do is setup an environment for compiling and elaborating our designs.  Any serious FPGA design will use libraries from the FPGA manufacturer for managing clock, DSP and memory resources.  My platform is the Xilinx Virtex5 FPGA, but the process explained here can be used for any platform.  Also, please note that I won’t cover how to prepare NCVerilog for use with Xilinx smartmodels used in modeling designs with IP cores.  If you’re trying to simulate FPGA designs with RapidIO, PCIe or CPRI IP cores, it is best to consult the documentation that comes with the IP core or with a vendor field application engineer.

Let us get started now.  From Appendix B of the Xilinx Synthesis and Simulation Design Guide, we have two choices for configuring NCVerilog.  We could instruct NCVerilog to use single-step mode and directly use the VHDL/Verilog source for the library.  But single-step mode combiles both compliation and elaboration, and I prefer to separate the two.  The other option is to use multi-step mode and  pre-compile the libraries ahead of time.  I’m going to go ahead and pre-compile them so I don’t have to constantly specify Xilinx libraries with each new project.

To pre-compile, one first has to run a Xilinx utility called compxlib.  There are several options for controlling the output, but I’m going to keep most of the defaults.  We only really need to specify the simulator, but I’m going to go further and limit my build to verilog libraries and the Virtex5 platform to save time.  On the command line of your workstation, exectue the following command.

compxlib -s ncsim -arch virtex5 -l verilog

If you’re ushing VHDL, replace “verilog” with “vhdl” in the above command.  For more about the options, use the help command provided with the tool or refer to Chapter 27 of Xilinx’s Development System Reference Guide.  The above command outputs to %XILINX%\verilog\ncsim, where %XILINX% is the environment variable for the Xilinx base directory.  %XILINX% would be $XILINX on Linux/UNIX.

One the compilation process ends, the next step is to update your library mapping configuration.  This is very easy to do, luckily.  I created a folder called ncsimcfg, and it is located in C:\work\ncsimcfg.  With your favorite text editor, create a new file in this directory and name it “xilinx_cds.lib”.  You can call it anything you like actually, but I’ll stick with xilinx_ cds.lib as it makes it clear this file is for designs using Xilinx libraries.

Now we have to fill in the library mapping. Let’s include the core libraries from Cadence first.  Add the following line to file:

include $CDS_INST_DIR\tools\inca\files\cds.lib

This includes Cadence’s libraries, such as their IEEE implementation and Cadence-specific primitives.  Next we need to add the Xilinx libraries.  There are the libraries that were created by compxlib in the beginning of this tutorial.

define simprims_ver $XILINX\verilog\ncsim\simprims_ver
define unimacro_ver $XILINX\verilog\ncsim\unimacro_ver
define unisims_ver $XILINX\verilog\ncsim\unisims_ver
define XilinxCoreLib_ver $XILINX\verilog\ncsim\XilinxCoreLib_ver

Please note that if your libraries are stored in a directory that has spaces in the path, you must enclose the path with quotation marks.  Save the cds.lib file because we’re through with it.

Next, create a file named “xilinx.src”, which will be a list of Xilinx verilog source that will need to be compile.  Again, you can name it anything, but I chose this name becaues it makes it clearer that the file relates to source code, and that it is also related to Xilinx.  In this file, for now,  we only have to insert one line:


If we later find that designs need other common files, we can add a new line with the path to the verilog source.  Now have two global files that we can share amongst our designs: a vendor-specific library mapping file and a vendor-specific source list.  If we have to support multiple FPGA vendors, we could create such a file for each vendor, such as “altera_cds.lib” and “altera.src”.

There is one more file that we must create.  It will be used in the elaboration process that I will cover later.  For now, in the same place as xilinx_cds.lib and xilinx.src, create a file named xilinx.elab.  In the file, insert the following line:


This just tells the elaboration process about the Xilinx glbl module. Finally, it is a good idea to run nchelp to enumerate your library mappings and make sure there aren’t any mistakes.

nchelp -cdslib C:\work\ncsimcfg\xilinx_cds.lib

As we can see on screen, the libraries we manually added are enumerated, and we can also see what the Cadence library mapping file including in our mapping file contains:

Defined in ..\Program Files\Cadence Design Systems\IUS\tools\inca\files\cdsvhdl.
Line #  Filesys            Verilog  VHDL               Path
——  ——-            ——-  —-               —-
1    std                std      STD                ..\Program Files\Cadence
Design Systems\IUS\tools\inca\files\STD
2    synopsys           synopsys  SYNOPSYS           ..\Program Files\Cadence
Design Systems\IUS\tools\inca\files\SYNOPSYS
3    ieee               ieee     IEEE               ..\Program Files\Cadence
Design Systems\IUS\tools\inca\files\IEEE
4    ambit              ambit    AMBIT              ..\Program Files\Cadence
Design Systems\IUS\tools\inca\files\AMBIT
5    vital_memory       vital_memory  VITAL_MEMORY       ..\Program Files\Cad
ence Design Systems\IUS\tools\inca\files\VITAL_MEMORY
6    ncutils            ncutils  NCUTILS            ..\Program Files\Cadence
Design Systems\IUS\tools\inca\files\NCUTILS
7    cds_assertions     cds_assertions  CDS_ASSERTIONS     ..\Program Files\C
adence Design Systems\IUS\tools\inca\files\CDS_ASSERTIONS

Defined in ..\Program Files\Cadence Design Systems\IUS\tools\ict\files\cds_ict.l
Line #  Filesys            Verilog  VHDL               Path
——  ——-            ——-  —-               —-
1    summit             summit   SUMMIT             ..\Program Files\Cadence
Design Systems\IUS\tools\ict\files\SUMMIT

This concludes the tutorial for now.  To recap everything, we pre-compile Xilinx’s libraries with xcomplib first.  We then create three global configuration files: xilinx.src, xilinx.elab and xilinx_cds.lib.  With these files in place we are ready to begin compiling, the subject of an entry to come.

Update on my Erlang experience

It has been awhile since I updated my blog.  I attribute it to work–the never ending stream of things to do kind of weights me down and I lose interest in all things technical from time to time.  I’m on a new project at work now, and I’m quite keen for it.  It’s still the same old low level C/Assembly firmware development, but I get to work with serial RapidIO technology and that has been quite interesting.  3.125 Gbps links!  I like this better than the former project working on MAC-layer software for a communication protocol.  I either want to be working at the PHY level directly accessing or working with the hardware, or I want to be up higher on the application level solving interesting problems.

Speaking of the application level, in late December I picked up my Erlang studies again, and I’m making good progress in understanding how to use it.  I’m implementing a simple chat server so I can wrap my mind around Erlang processes, file I/O and TCP sockets.  Having programmed a server in C/C++ before I can really appreciate how great Erlang is for network computing.  The code is so much more concise than the multithreaded C++ server I wrote in the past.  I’m not using the Erlang OTP libraries yet, I’m working with the gen_tcp library since it is familiar to BSD-style socket programming.  I’ve even dabled in a some Python scripts for testing the server.  Like how Perl has become my tool of choice for “glueing” things together, I can see myself using Python more often for testing in the future.  

Progress has been good, but I feel really shaky with strings at the moment.  Manipulating text is something any software has to do, but I find that the first thing that pops to my mind is the C++ STL string library, so I go searching for a similar library in the Erlang man pages.  I suppose that this must be expected–I just don’t know which libraries to use yet and it will take time to get the hang of them.  It took me awhile to master the use of the C++ STL string library and its algorithms, and I’m just going to have to figure out which Erlang libraries have the functions I need.  Perhaps I’ll draft a tutorial on Erlang string processing if I learn enough?

The good news is that my confidence with the language is increasing, tail recursion doesn’t seem that awkward, and immutable variables make complete sense now.  I won’t be using Erlang at work any time soon (not the right problem domain), but for personal enrichment and for learning new ways of doing things I’m quite pleased with Erlang. If I ever get into application network programming (or network services), I know what tool I’ll be choosing.