On Verilog compilers

I’ve been working on my term project for my ASIC design course, and one thing I find very disturbing is the difference in error discovery between various Verilog compilers.  My design compiled correctly with ModelSim’s vlog compiler, but GNU Icarus Verilog caught errors that ModelSim did not.  After fixing the issues I then ran my Verilog through Synopsys Design Compiler so that I could synthesize the design.  Interestingly, Design Compiler caught some rather serious bugs that both ModelSim and Icarus missed.

If I ever start my own chip design company, I will definitely invest in a Synopsys license!  It would also be interesting to run the verilog model with the errors through FPGA Verilog compilers like Xilinx or Lattice and see if those tools can catch the same errors as Design Compiler.  I have no time for that right now though…

Using C++0x features with g++

With the announcement recently that the C++0x spec has finally been finalized–I suppose it should be called C++11 at this point–I will now try to learn more of the new features that will be available.  I happy that much of what I currently use in Boost will become standardized (such as shared_ptr, threads, etc.)

Just as an FYI to myself, to play with C++0x features in g++, add the “-std=gnu++0x” compiler option.  For example, it get the following program to build:

// decltype.cpp
int f() { return 0; }

int main()
{
   decltype(f()) i = 8;
   return 0;
}

use the following on the command line:

g++ -std=gnu++0x decltype.cp